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DSP56F802/d rev. 6.0 , 02/2004 ? motorola, inc., 2004. all rights reserved. 56f802 technical data 56f802 16-bit hybrid controller ? up to 30 mips operation at 60mhz core frequency up to 40 mips operation at 80mhz core frequency dsp and mcu functionality in a unified, c-efficient architecture mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes hardware do and rep loops 6-channel pwm module with fault input two 12-bit adcs (1 x 2 channel, 1 x 3 channel) serial communications interface (sci) 8k 16-bit words program flash 1k 16-bit words program ram 2k 16-bit words data flash 1k 16-bit words data ram 2k 16-bit words boot flash two general purpose quad timers with 2 external outputs jtag/once tm port for debugging 4 shared gpio on-chip relaxation oscillator 32-pin lqfp package figure 1. 56f802 block diagram jtag/ once port digital reg analog reg low voltage supervisor program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers two 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800 core pab pdb xdb2 cgdb xab1 xab2 interrupt controls ipbb controls ipbus bridge (ipbb) module controls address bus [8:0] data bus [15:0] cop reset reset application- specific memory & peripherals interrupt controller program memory 8188 x 16 flash 1024 x 16 sram boot flash 2048x 16 flash data memory 2048 x 16 flash 1024 x 16 sram cop/ watchdog sci0 or gpio quad timer d or gpio quad timer c a/d1 a/d2 adc 2 2 3 2 6 pwm outputs pwma 16 16 vcapc v dd v ss *v dda v ssa 5 22 3 ? ? ? ? ? ? ? ? vref pll relaxation oscillator . * includes tcs pin which is reserved for factory use and is tied to vss fault a0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 56f802 technical data part 1 overview 1.1 56f802 features 1.1.1 digital signal processing core efficient 16-bit 56800 family hybrid controller engine with dual harvard architecture as many as 40 million instructions per second (mips) at 80 mhz core frequency single-cycle 16 16-bit parallel multiplier-accumulator (mac) two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter parallel instruction set with unique dsp addressing modes hardware do and rep loops three internal address buses and one external address bus four internal data buses and one external data bus instruction set supports both dsp and controller functions controller style addressing modes and instructions for compact code efficient c compiler and local variable support software subroutine and interrupt stack with depth limited only by memory jtag/once debug programming interface 1.1.2 memory harvard architecture permits as many as three simultaneous accesses to program and data memory on-chip memory including a low-cost, high-volume flash solution ? 8k 16 bit words of program flash ? 1k 16-bit words of program ram ? 2k 16-bit words of data flash ? 1k 16-bit words of data ram ? 2k 16-bit words of boot flash programmable boot flash supports customized boot code and field upgrades of stored code through a variety of interfaces (jtag) 1.1.3 peripheral circuits for 56f802 pulse width modulator (pwm) with six pwm outputs with deadtime insertion and fault protection; supports both center- and edge-aligned modes two 12-bit, analog-to-digital converters (adcs), 1 x 2 channel and 1 x 3 channel, which support two simultaneous conversions; adc and pwm modules can be synchronized two general purpose quad timers with two external pins (or two gpio) serial communication interface (sci) with two pins (or two gpio) four multiplexed general purpose i/o (gpio) pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
56f802 description 56f802 technical data 3 computer-operating properly (cop) watchdog timer external interrupts via gpio trimmable on-chip relaxation oscillator external reset pin for hardware reset jtag/on-chip emulation (once ? ) for unobtrusive, processor speed-independent debugging software-programmable, phase locked loop-based frequency synthesizer for the hybrid controller core clock 1.1.4 energy information fabricated in high-density cmos with 5v-tolerant, ttl-compatible digital inputs uses a single 3.3v power supply on-chip regulators for digital and analog circuitry to lower cost and reduce noise wait and stop modes available integrated power supervisor 1.2 56f802 description the 56f802 is a member of the 56800 core-based family of hybrid controllers. it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the 56f802 is well-suited for many applications. the 56f802 includes many peripherals that are especially useful for applications such as motion control, home appliances, encoders, tachometers, limit switches, power supply and control, engine management, and industrial control for power, lighting, automation and hvac. the 56800 core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the 56f802 supports program execution from either internal or external memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the 56f802 also provides and up to 4 general purpose input/output (gpio) lines, depending on peripheral configuration. the 56f802 controller includes 8k words (16-bit) of program flash and 2k words of data flash (each programmable through the jtag port) with 1k words of both program and data ram. a total of 2k words of boot flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main program and data flash memory areas. both program and data flash memories can be independently bulk erased or erased in page sizes of 256 words. the boot flash memory can also be either bulk or page erased. a key application-specific feature of the 56f802 is the inclusion of a pulse width modulator (pwm) module. this modules incorporates six complementary, individually programmable pwm signal outputs to enhance motor control functionality. complementary operation permits programmable dead-time insertion, and separate top and bottom output polarity control. the up-counter value is programmable to support a continuously variable pwm frequency. both edge- and center-aligned synchronous pulse width control (0% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 56f802 technical data to 100% modulation) are supported. the device is capable of controlling most motor types: acim (ac induction motors), both bdc and bldc (brush and brushless dc motors), srm and vrm (switched and variable reluctance motors), and stepper motors. the pwms incorporate fault protection with sufficient output drive capability to directly drive standard opto-isolators. a ? smoke-inhibit ? , write-once protection feature for key parameters is also included. the pwm is double-buffered and includes interrupt control to permit integral reload rates to be programmable from 1 to 16. the pwm modules provide a reference output to synchronize the analog-to-digital converters. the 56f802 incorporates two 12-bit analog-to-digital converters (adcs) with a total of five channels. a full set of standard programmable peripherals is provided that include a serial communications interface (sci), and two quad timers. any of these interfaces can be used as general-purpose input/outputs (gpio) if that function is not required. an on-chip relaxation oscillator eliminates the need for an external crystal. 1.3 state of the art development environment processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to- use component-based software application creation with an expert knowledge system. the code warrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards will support concurrent engineering. together, pe, code warrior and evms create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 product documentation the four documents listed in table 1 are required for a complete description and proper design with the 56f802. documentation is available from local motorola distributors, motorola semiconductor sales offices, motorola literature distribution centers, or online at www.motorola.com/semiconductors . table 1. 56f802 chip documentation topic description order number dsp56800 family manual detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set dsp56800fm/d dsp56f801/803/805/807 user?s manual detailed description of memory, peripherals, and interfaces of the 56f801, 56f802, 56f803, 56f805, and 56f807 dsp56f801-7um/d 56f802 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56F802/d 56f802 product brief summary description and block diagram of the 56f802 core, memory, peripherals and interfaces DSP56F802pb/d DSP56F802 errata details any chip issues that might be present DSP56F802e/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data sheet conventions 56f802 technical data 5 1.5 data sheet conventions this data sheet uses the following conventions: overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ? asserted ? a high true (active high) signal is high or a low true (active low) signal is low. ? deasserted ? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for v il , v ol , v ih , and v oh are defined by individual product specifications pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 56f802 technical data part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56f802 are organized into functional groups, as shown in table 2 and as illustrated in figure 2 . in table 3 through table 11 , each table row describes the signal or signals present on a pin. table 2. functional group pin allocations functional group number of pins detailed description power (v dd or v dda )3 table 3 ground (v ss, v ssa, tcs) 4 table 4 supply capacitors 2 table 5 program control 1 table 6 pulse width modulator (pwm) port and fault input 7 table 7 serial communications interface (sci) port 1 1. alternately, gpio pins 2 table 8 analog-to-digital converter (adc) port (including v ref) 6 table 9 quad timer module port 2 table 10 jtag/on-chip emulation (once) 5 table 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction 56f802 technical data 7 figure 2. 56f802 signals identified by functional group 1 1. alternate pin functionality is shown in parenthesis. 56f802 power port ground port power port ground port sci0 port or gpio v dd v ss v dda v ssa vcapc tck tms tdi tdo trst jtag/ once ? port pwma0-5 fault a0 txd0 (gpiob0) rxd0 (gpiob1) ana2-4, ana6-7 vref td1-2 (gpioa1-2) reset quad timer d or gpio adca port other supply port 2 3* 1 1 2 1 1 1 1 1 program control 6 1 1 1 5 1 2 1 * includes tcs pin which is reserved for factory use and is tied to vss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 56f802 technical data 2.2 power and ground signals 2.3 interrupt and program control signals table 3. power inputs no. of pins signal name signal description 2 v dd power ? these pins provide power to the internal structures of the chip, and should all be attached to v dd. 1 v dda analog power ? this pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3v supply. table 4. grounds no. of pins signal name signal description 2 v ss gnd ? these pins provide grounding for the internal structures of the chip, and should all be attached to v ss. 1 v ssa analog ground ? this pin supplies an analog ground. 1 tcs tcs ? this schmitt pin is reserved for factory use and must be tied to v ss for normal use. in block diagrams, this pin is considered an additional v ss. table 5. supply capacitors and vpp no. of pins signal name signal type state during reset signal description 2 vcapc supply supply vcapc ? connect each pin to a 2.2 f or greater bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). for more information, refer to section 5.2 table 6. program control signals no. of pins signal name signal type state during reset signal description 1 reset input (schmitt) input reset ? this input is a direct hardware reset on the processor. when reset is asserted low, the hybrid controller is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the extboot pin. the internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the once/jtag module. in this case, assert reset , but do not assert trst . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pulse width modulator (pwm) signals 56f802 technical data 9 2.4 pulse width modulator (pwm) signals 2.5 serial communications interface (sci) signals 2.6 analog-to-digital converter (adc) signals table 7. pulse width modulator (pwma) signals no. of pins signal name signal type state during reset signal description 6 pwma0-5 output tri-stated pwma0-5 ? these are six pwma output pins. 1 faulta0 input (schmitt) input faulta0 ? this fault input is used for disabling selected pwma outputs in cases where fault conditions originate off- chip. table 8. serial communications interface (sci0) signals no. of pins signal name signal type state during reset signal description 1 txd0 gpiob0 output input/ output input input transmit data (txd0) ? sci0 transmit data output port b gpio ? this pin is a general purpose i/o (gpio) pin that can be individually programmed as an input or output pin. after reset, the default state is sci output. 1 rxd0 gpiob1 input input/ output input input receive data (rxd0) ? sci0 receive data input port b gpio ? this pin is a general purpose i/o (gpio) pin that can be individually programmed as an input or output pin. after reset, the default state is sci input. table 9. analog to digital converter signals no. of pins signal name signal type state during reset signal description 3 ana2-4 input input ana2-4 ? analog inputs to adc, channel 1 2 ana6-7 input input ana6-7 ? analog inputs to adc, channel 2 1 vref input input vref ? analog reference voltage. must be set to v dda - 0.3v for optimal performance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 56f802 technical data 2.7 quad timer module signals 2.8 jtag/once table 10. quad timer module signals no. of pins signal name signal type state during reset signal description 2 td1-2 gpioa1-2 input/ output input/ output input input td1-2 ? timer d channel 1-2 port a gpio ? these pins are general purpose i/o (gpio) pins that can be individually programmed as input or output pins. after reset, the default state is the quad timer input. table 11. jtag/on-chip emulation (once) signals no. of pins signal name signal type state during reset signal description 1 tck input (schmitt) input, pulled low internally test clock input ? this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/once port. the pin is connected internally to a pull-down resistor. 1 tms input (schmitt) input, pulled high internally test mode select input ? this input pin is used to sequence the jtag tap controller ? s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 1 tdi input (schmitt) input, pulled high internally test data input ? this input pin provides a serial input data stream to the jtag/once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 1 tdo output tri-stated test data output ? this tri-statable output pin provides a serial output data stream from the jtag/once port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. 1 trst input (schmitt) input, pulled high internally test reset ? as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted at power-up and whenever reset is asserted. the only exception occurs in a debugging environment, since the once/jtag module is under the control of the debugger. in this case it is not necessary to assert trst when asserting reset . outside of a debugging environment reset should be permanently asserted by grounding the signal, thus disabling the once/jtag module on the device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general characteristics 56f802 technical data 11 part 3 specifications 3.1 general characteristics the 56f802 is fabricated in high-density cmos with 5-volt tolerant ttl-compatible digital inputs. the term ? 5-volt tolerant ? refers to the capability of an i/o pin, built on a 3.3v compatible process technology, to withstand a voltage up to 5.5v without damaging the device. many systems have a mixture of devices designed for 3.3v and 5v power supplies. in such systems, a bus may carry both 3.3v and 5v- compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operation without causing damage). this 5v-tolerant capability therefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels without being damaged. absolute maximum ratings given in table 12 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the 56f802 dc and ac electrical specifications are preliminary and are from design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published after complete characterization and device qualifications have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 12. absolute maximum ratings characteristic symbol min max unit supply voltage v dd v ss ? 0.3 v ss + 4.0 v all other input voltages, excluding analog inputs v in v ss ? 0.3 v ss + 5.5v v analog inputs anax, v ref v in v ss ? 0.3 v dda + 0.3v v current drain per pin excluding v dd , v ss , & pwm ouputs i ? 10 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12 56f802 technical data notes: 1. theta-ja determined on 2s2p test boards is frequently lower than would be observed in an application. determined on 2s2p thermal test board. 2. junction to ambient thermal resistance, theta-ja ( r ja ) was simulated to be equivalent to the jedec specification jesd51-2 in a horizontal configuration in natural convection. theta-ja was also simulated on a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number of planes) per jesd51-6 and jesd51-7. the correct name for theta-ja for forced convection or with the non-single layer boards is theta-jma. 3. junction to case thermal resistance, theta-jc (r jc ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. the basic cold plate measurement technique is described by mil-std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. thermal characterization parameter, psi-jt ( jt ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in jesd51-2. jt is a useful value to use to estimate junction temperature in steady state customer environments. table 13. recommended operating conditions characteristic symbol min typ max unit supply voltage, digital v dd 3.0 3.3 3.6 v supply voltage, analog v dda 3.0 3.3 3.6 v adc reference voltage vref 2.7 ? v dda v ambient operating temperature t a ? 40 ? 85 c table 14. thermal characteristics 6 characteristic comments symbol value unit note s 32-pin lqfp junction to ambient natural convection r ja 50.2 c/w 2 junction to ambient (@1m/sec) r jma 47.1 c/w 2 junction to ambient natural convection four layer board (2s2p) r jma (2s2p) 38.7 c/w 1,2 junction to ambient (@1m/sec) four layer board (2s2p) r jma 37.4 c/w 1,2 junction to case r jc 17.8 c/w 3 junction to center of case jt 3.07 c/w 4 i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd x v dd + p i/o )w junction to center of case p dmax (tj - ta) / ja c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
dc electrical characteristics 56f802 technical data 13 5. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. see section 5.1 from more details on thermal design considerations. 3.2 dc electrical characteristics table 15. dc electrical characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0 ? 3.6 v, t a = ? 40 to +85 c, c l 50pf characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc 2.25 ? 2.75 v input low voltage (xtal/extal) v ilc 0 ? 0.5 v input high voltage (schmitt trigger inputs) 1 v ihs 2.2 ? 5.5 v input low voltage (schmitt trigger inputs) 1 v ils -0.3 ? 0.8 v input high voltage (all other digital inputs) v ih 2.0 ? 5.5 v input low voltage (all other digital inputs) v il -0.3 ? 0.8 v input current high (pullup/pulldown resistors disabled, v in =v dd ) i ih -1 ? 1 a input current low (pullup/pulldown resistors disabled, v in =v ss ) i il -1 ? 1 a input current high (with pullup resistor, v in =v dd )i ihpu -1 ? 1 a input current low (with pullup resistor, v in =v ss )i ilpu -210 ? -50 a input current high (with pulldown resistor, v in =v dd )i ihpd 20 ? 180 a input current low (with pulldown resistor, v in =v ss )i ilpd -1 ? 1 a nominal pullup or pulldown resistor value r pu , r pd 30 k ? output tri-state current low i ozl -10 ? 10 a output tri-state current high i ozh -10 ? 10 a input current high (analog inputs, v in =v dda ) 2 i iha -15 ? 15 a input current low (analog inputs, v in =v ssa ) 2 i ila -15 ? 15 a output high voltage (at ioh) v oh v dd ? 0.7 ?? v output low voltage (at iol) v ol ?? 0.4 v output source current i oh 4 ?? ma output sink current i ol 4 ?? ma pwm pin output source current 3 i ohp 10 ?? ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14 56f802 technical data pwm pin output sink current 4 i olp 16 ?? ma input capacitance c in ? 8 ? pf output capacitance c out ? 12 ? pf v dd supply current i ddt 5 run 6 (80mhz operation) ? 120 130 ma run 6 (60mhz operation) ? 102 111 ma wait 7 ? 96 102 ma stop ? 62 70 ma low voltage interrupt, external power supply 8 v eio 2.4 2.7 3.0 v low voltage interrupt, internal power supply 9 v eic 2.0 2.2 2.4 v power on reset 10 v por ? 1.7 2.0 v 1. schmitt trigger inputs are: faulta0, tcs, tck, tms, tdi, reset , and trst 2. analog inputs are: ana[0:7], xtal and extal. specification assumes adc is not sampling. 3. pwm pin output source current measured with 50% duty cycle. 4. pwm pin output sink current measured with 50% duty cycle. 5. i ddt = i dd + i dda (total supply current for v dd + v dda ) 6. run (operating) i dd measured using 8mhz clock source. all inputs 0.2v from rail; outputs unloaded. all ports configured as inputs; measured with all modules enabled. 7. wait i dd measured using external square wave clock source (f osc = 8mhz) into xtal; all inputs 0.2v from rail; no dc loads; less than 50pf on all outputs. c l = 20pf on extal; all ports configured as inputs; extal capacitance linearly affects wait i dd ; measured with pll enabled. 8. this low voltage interrupt monitors the v dda external power supply. v dda is generally connected to the same potential as v dd via separate traces. if v dda drops below v eio , an interrupt is generated. functionality of the device is guaranteed under transient conditions when v dda > v eio (between the minimum specified v dd and the point when the v eio interrupt is generated). 9. this low voltage interrupt monitors the internally regulated core power supply. if the output from the internal voltage is regulator drops below v eic , an interrupt is generated. since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0v). 10. power ? on reset occurs whenever the internally regulated 2.5v digital supply drops below 1.5v typical. while power is ramping up, this signal remains active for as long as the internal 2.5v is below 1.5v typical no matter how long the ramp up rate is. the internally regulated voltage is typically 100 mv less than v dd during ramp up until 2.5v is reached, at which time it self regulates. table 15. dc electrical characteristics (continued) operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0 ? 3.6 v, t a = ? 40 to +85 c, c l 50pf characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac electrical characteristics 56f802 technical data 15 figure 3. maximum run idd vs. frequency (see note 6. in table 15 ) 3.3 ac electrical characteristics timing waveforms in section 3.3 are tested using the v il and v ih levels specified in the dc characteristics table. in figure 4 the levels of v ih and v il for an input signal are shown. figure 4. input signal measurement references figure 5 shows the definitions of the following signal states: active state, when a bus or signal is driven, and enters a low impedance state. tri-stated, when a bus or signal is placed in a high impedance state. data valid state, when a signal level has reached v ol or v oh. data invalid state, when a signal level is in transition between v ol and v oh. 0 40 80 120 160 10 20 30 40 50 60 70 80 freq. (mhz) idd (ma) idd digital idd analog idd total v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16 56f802 technical data 3.4 flash memory characteristics figure 5. signal states table 16. flash memory truth table mode xe 1 1. x address enable, all rows are disabled when xe = 0 ye 2 2. y address enable, ymux is disabled when ye = 0 se 3 3. sense amplifier enable oe 4 4. output enable, tri-state flash data out bus when oe = 0 prog 5 5. defines program cycle erase 6 6. defines erase cycle mas1 7 7. defines mass erase cycle, erase whole block nvstr 8 8. defines non-volatile store cycle standby l l l l l l l l read h h h h l l l l word program h h l l h l l h page erase h l l l l h l h mass erase h l l l l h h h table 17. ifren truth table mode ifren = 1 ifren = 0 read read information block read main memory block word program program information block program main memory block page erase erase information block erase main memory block mass erase erase both blocks erase main memory block data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
flash memory characteristics 56f802 technical data 17 table 18. flash timing parameters operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0 ? 3.6v, t a = ? 40 to +85 c, c l 50pf characteristic symbol min typ max unit figure program time t prog* 20 ?? us figure 6 erase time t erase* 20 ?? ms figure 7 mass erase time t me* 100 ?? ms figure 8 endurance 1 1. one cycle is equal to an erase program and read. e cyc 10,000 20,000 ? cycles data retention 1 @ 5000 cycles d ret 10 30 ? years the following parameters should only be used in the manual word programming mode prog/erase to nvstr set up time t nvs* ? 5 ? us figure 6 , figure 7 , figure 8 nvstr hold time t nvh* ? 5 ? us figure 6 , figure 7 nvstr hold time (mass erase) t nvh1* ? 100 ? us figure 8 nvstr to program set up time t pgs* ? 10 ? us figure 6 recovery time t rcv* ? 1 ? us figure 6 , figure 7 , figure 8 cumulative program hv period 2 2. thv is the cumulative high voltage programming time to the same row before next erase. the same address cannot be programmed twice before next erase. t hv ? 3 ? ms figure 6 program hold time 3 3. parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *the flash interface unit provides registers for the control of these parameters. t pgh ??? figure 6 address/data set up time 3 t ads ??? figure 6 address/data hold time 3 t adh ??? figure 6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18 56f802 technical data figure 6. flash program cycle figure 7. flash erase cycle xadr yadr ye din prog nvstr tnvs tpgs tadh tprog tads tpgh tnvh trcv thv ifren xe xadr ye=se=oe=mas1=0 erase nvstr tnvs tnvh trcv terase ifren xe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
clock operation 56f802 technical data 19 figure 8. flash mass erase cycle 3.5 clock operation the 56f802 device clock is derived from an on-chip relaxation oscillator. the internal pll generates a master reference frequency that determines the speed at which chip operations occur. the precs bit in the pllcr (phase-locked loop control register) word (bit 2) must be set to 0 for internal oscillator use. 3.5.1 use of on-chip relaxation oscillator the 56f802 internal relaxation oscillator provides the chip clock without the need for an external crystal or ceramic resonator. the frequency output of this internal oscillator can be corrected by adjusting the 8-bit iosctl (internal oscillator control) register. each bit added or deleted changes the output frequency of the oscillator allowing incremental adjustment until the desired frequency is achieved. figures 9 and 10 show the typical characteristics of the 56f802 relaxation oscillator with respect to temperature and trim value. during factory production test, an oscillator calibration procedure is executed which determines an optimum trim value for a given device (8mhz at 25 o c). this optimum trim value is then stored at address $103f in the data flash information block and recalled during a trim routine in the boot sequence (executed after power-up and reset). this trim routine automatically sets the oscillator frequency by programming the iosctl register with the optimum trim value. due to the inherent frequency tolerances required for sci communication, changing the factory-trimmed oscillator frequency is not recommended. if modification of the boot flash contents are required, code must be included which retrieves the optimum trim value (from address $103f in the data flash information block) and writes it to the iosctl register. note that the ifren bit in the data flash control register must be set in order to read the data flash information block. xadr ye=se=oe=0 erase nvstr tnvs tnvh1 trcv tme mas1 ifren xe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20 56f802 technical data figure 9. typical relaxation oscillator frequency vs. temperature (trimmed to 8mhz @ 25 o c) table 19. relaxation oscillator characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0 ? 3.6 v, t a = ? 40 to +85 c characteristic symbol min typ max unit frequency accuracy 1 1. over full temperature range. ? f ? + 2+ 5% frequency drift over temp ? f/ ? t ? + 0.1 ? %/ o c frequency drift over supply ? f/ ? v ? 0.1 ? %/v 8.2 8.0 8.3 8.4 7.9 8.1 7.8 75 55 -40 35 -25 15 -5 85 temperature ( o c) output frequency f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
clock operation 56f802 technical data 21 figure 10. typical relaxation oscillator frequency vs. trim value @ 25 o c 3.5.2 phase locked loop timing table 20. pll timing characteristic symbol min typ max unit frequency for the pll 1 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8mhz input crystal. 2. zclk may not exceed 80mhz. for additional information on zclk and f out /2, please refer to the occs chapter in the user manual. zclk = f op 3. will not exceed 60mhz for the DSP56F802ta60 device. 4. this is the minimum time required after the pll setup is changed to ensure reliable operation. f osc 4810mhz pll output frequency 2 f out /2 40 ? 80 3 mhz pll stabilization time 4 0 o to +85 o c t plls ? 10 ? ms pll stabilization time 4 -40 o to 0 o c t plls ? 100 200 ms 0 102030405060708090a0b0c0d0e0f0 5 6 7 8 9 10 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
22 56f802 technical data 3.6 reset, stop, wait, mode select, and interrupt timing figure 11. external level-sensitive interrupt timing 3.7 quad timer timing table 21. reset, stop, wait, mode select, and interrupt timing 1, 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0 ? 3.6 v, t a = ? 40 to +85 c, c l 50pf 1. in the formulas, t = clock cycle. for an operating frequency of 80mhz, t = 12.5ns. characteristic symbol min max unit reset assertion to address, data and control signals high impedance t raz ? 21 ns minimum reset assertion duration 2 omr bit 6 = 0 omr bit 6 = 1 2. circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: after power-on reset when recovering from stop state 3. parameters listed are guaranteed by design. t ra 275,000t 128t ? ? ns ns reset de-assertion to first external address output t rda 33t 34t ns edge-sensitive interrupt request width t irw 1.5t ? ns table 22. timer timing 1, 2 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0 ? 3.6 v, t a = ? 40 to +85 c, c l 50pf 1. in the formulas listed, t = clock cycle. for 80mhz operation, t = 12.5 ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit timer input period p in 4t+6 ? ns timer input high/low period p inhl 2t+3 ? ns timer output period p out 2t ? ns timer output high/low period p outhl 1t ? ns general purpose i/o pin irqa b) general purpose i/o t ig f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communication interface (sci) timing 56f802 technical data 23 3.8 serial communication interface (sci) timing figure 13. rxd pulse width figure 14. txd pulse width figure 12. timer timing table 23. sci timing 4 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0 ? 3.6 v, t a = ? 40 to +85 c, c l 50pf characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br ? (f max *2.5)/(80) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns timer inputs timer outputs p outhl p outhl p out p in p inhl p inhl rxd sci receive data pin (input) rxd pw txd sci receive data pin (input) txd pw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
24 56f802 technical data 3.9 analog-to-digital converter (adc) characteristics table 24. adc characteristics operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0 ? 3.6 v, v ref = v dd -0.3v, adcdiv = 4, 9, or 14,(for optimal performance), adc clock = 4mhz, 3.0 ? 3.6 v, t a = ? 40 to +85 c, c l 50pf characteristic symbol min typ max unit adc input voltages v adcin 0 1 1. for optimum adc performance,keep the minimum v adcin value > 250mv. inputs less than 250mv volts may convert to a digital output code of 0 or cause erroneous conversions. ? v ref 2 2. v ref must be equal to or less than v dda and must be greater than 2.7v. for optimal adc performance, set v ref to v dda -0.3v. v resolution r es 12 ? 12 bits integral non-linearity 3 3. measured in 10-90% range. inl ? +/- 4 +/- 5 lsb 4 4. lsb = least significant bit. differential non-linearity dnl ? +/- 0.9 +/- 1 lsb 3 monotonicity guaranteed adc internal clock 5 5. guaranteed by characterization. f adic 0.5 ? 5mhz conversion range r ad v ssa ? v dda v power-up time t adpu ? 2.5 ? msec conversion time t adc ? 6 ? t aic cycles 6 6. t aic = 1/ f adic sample time t ads ? 1 ? t aic cycles 6 input capacitance c adi ? 5 ? pf 6 gain error (transfer gain) 5 e gain 1.00 1.10 1.15 ? offset voltage 5 v offset +10 +230 +325 mv total harmonic distortion 5 thd 55 60 ? db signal-to-noise plus distortion 5 sinad 54 56 ?? effective number of bits 5 enob 8.5 9.5 ? bit spurious free dynamic range 5 sfdr 60 65 ? db spurious free dynamic range sfdr 65 70 ? db adc quiescent current (both adcs) i adc ? 50 ? ma v ref quiescent current (both adcs) i vref ? 12 16.5 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
jtag timing 56f802 technical data 25 figure 15. equivalent analog input circuit 1. parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf) 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing. (2.04pf) 3. equivalent resistance for the esd isolation resistor and the channel select mux. (500 ohms) 4. sampling capacitor at the sample and hold circuit. capacitor 4 is normally disconnected from the input and is only connected to it at sampling time. (1pf) 3.10 jtag timing table 25. jtag timing 1, 3 operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0 ? 3.6 v, t a = ? 40 to +85 c, c l 50 pf 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for 80mhz operation, t = 12.5ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/8 the processor rate. 3. parameters listed are guaranteed by design. f op dc 10 mhz tck cycle time t cy 100 ? ns tck clock pulse width t pw 50 ? ns tms, tdi data setup time t ds 0.4 ? ns tms, tdi data hold time t dh 1.2 ? ns tck low to tdo data valid t dv ? 26.6 ns tck low to tdo tri-state t ts ? 23.5 ns trst assertion time t trst 50 ? ns 1 2 3 4 adc analog input f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
26 56f802 technical data figure 16. test clock input timing diagram figure 17. test access port timing diagram figure 18. trst timing diagram tck (input) v m v il v m = v il + (v ih ? v il )/2 v m v ih t pw t pw t cy input data valid output data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms t dv t dv t ts t ds t dh trst (input) t trst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
package and pin-out information 56f802 56f802 technical data 27 part 4 packaging 4.1 package and pin-out information 56f802 this section contains package and pin-out information for the 32-pin lqfp configuration of the 56f802. figure 19. top view, 56f802 32-pin lqfp package table 26. 56f802 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1pwma49 tcs 17 v dda 25 ana4 2pwma510 tck 18 v ssa 26 ana6 3td111tms19v dd 27 ana7 pin 1 orientation mark pwma4 pwma5 td1 td2 txdo v ss v dd rxd0 tcs tck tms tdi vcapc2 tdo trst reset ana3 vref ana2 faulta0 v ss v dd v ssa v dda pwma3 pwma2 pwma1 vcapc1 pwma0 ana7 ana6 ana4 pin 25 pin 1 7 motorola 56f802 pin 9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
28 56f802 technical data figure 20. 32-pin lqfp mechanical information (case 873a) 4td212tdi20v ss 28 pwma0 5 txdo 13 vcapc2 21 faulta0 29 vcapc1 6v ss 14 tdo 22ana230pwma1 7v dd 15 trst 23 vref 31 pwma2 8 rxd0 16 reset 24 ana3 32 pwma3 table 26. 56f802 pin identification by pin number (continued) pin no. signal name pin no. signal name pin no. signal name pin no. signal name notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. datum plane a, b and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimensions b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more then 0.08 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protursion: 0.07 mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1 mm and 0.25 mm from the lead tip. dim a min max millimeters a1 a2 b b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 7.00 bsc e e e1 l1 1.00 ref o 07 o1 12 l 0.70 r1 0.08 0.20 r2 1.40 1.60 0.05 1.45 0.15 1.35 0.45 0.30 9.00 bsc s 0.20 ref 0.80 bsc 9.00 bsc 7.00 bsc 0.50 ref 0.08 -- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
thermal design considerations 56f802 technical data 29 part 5 design considerations 5.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature c r ja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (pcb), or otherwise change the thermal dissipation capability of the area surrounding the device on the pcb. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. definitions: a complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junction to board thermal resistance. use the value obtained by the equation (t j ? t t )/p d where t t is the temperature of the package case determined by a thermocouple. t j t a p d r ja () + = r ja r jc r ca + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
30 56f802 technical data the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. from this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. 5.2 electrical design considerations use the following list of considerations to assure correct operation: provide a low-impedance path from the board power supply to each v dd pin on the hybrid controller, and from the board ground to each v ss (gnd) pin. the minimum bypass requirement is to place 0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capacitors tend to provide better performance tolerances. ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead. bypass the v dd and v ss layers of the pcb with approximately 100 f, preferably with ceramic or tantalum capacitors which tend to provide better performance tolerances. because the controller ? s output signals have fast rise and fall times, pcb trace lengths should be minimal. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical design considerations 56f802 technical data 31 consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and gnd circuits. take special care to minimize noise levels on the vref, v dda and v ssa pins. designs that utilize the trst pin for jtag port or once module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . trst must be asserted at power up for proper operation. designs that do not require debugging functionality, such as consumer products, trst should be tied low. because the flash memory is programmed through the jtag/once port, designers should provide an interface to this port to allow in-circuit flash programming. part 6 ordering information table 27 lists the pertinent information needed to place an order. consult a motorola semiconductor sales office or authorized distributor to determine availability and to order parts. table 27. 56f802 ordering information part supply voltage package type pin count frequency (mhz) order number 56f802 3.0 ? 3.6 v low profile plastic quad flat pack (lqfp) 32 80 DSP56F802ta80 56f802 3.0 ? 3.6 v low profile plastic quad flat pack (lqfp) 32 60 DSP56F802ta60 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 home page: http://motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2004 DSP56F802/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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